pdu5 4 doc #98004 data delay devices, inc. 1 3/18/98 3 mt. prospect ave. clifton, nj 07013 4-bit, ecl-interfaced programmable delay line (series pdu54) features packages digitally programmable in 16 delay steps monotonic delay-versus-address variation precise and stable delays input & outputs fully 100k-ecl interfaced & buffered available in 24-pin dip (600 mil) socket or smd functional description the pdu54-series device is a 4-bit digitally programmable delay line. the delay, td a , from the input pin (in) to the output pin (out) depends on the address code (a3-a0) according to the following formula: td a = td 0 + t inc * a where a is the address code, t inc is the incremental delay of the device, and td 0 is the inherent delay of the device. the incremental delay is specified by the dash number of the device and can range from 100ps through 3000ps, inclusively. the address is not latched and must remain asserted during normal operation. series specifications total programmed delay tolerance: 5% or 40ps, whichever is greater inherent delay (td 0 ): 3.3 ns typical address to input setup (t a is ): 2.9ns operating temperature: 0 to 85 c temperature coefficient: 100ppm/ c (excludes td 0 ) supply voltage v ee : -5vdc 0.7v power supply current: -300ma typical (50 w to -2v) minimum pulse width: 3ns or 10% of total delay, whichever is greater minimum period: 8ns or 2 x pulse width, whichever is greater t oax pw in td a pw out a3-a0 in out figure 1: timing diagram a i-1 a i t ais 1997 data delay devices data delay devices, inc. 3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 n/c n/c gnd n/c n/c n/c n/c n/c gnd out n/c n/c in n/c vee a3 n/c n/c a2 a1 vee a0 n/c n/c 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 n/c n/c gnd n/c n/c n/c n/c n/c gnd out n/c n/c in n/c vee a3 n/c n/c a2 a1 vee a0 n/c n/c pdu54-xx dip pdu54-xxm military dip pdu54-xxc4 smd pdu54-xxmc4 mil smd pin descriptions in signal input out signal output a3-a0 address bit s vee -5 volts gnd ground dash number specifications part number incremental delay per step ( ps) total delay change ( ns) pdu54-100 100 50 1.50 pdu54-200 200 60 3.00 pdu54-250 250 60 3.75 pdu54-400 400 80 6.00 pdu54-500 500 100 7.50 pdu54-750 750 100 11.25 pdu54-1000 1000 200 15.00 pdu54-1200 1200 200 18.00 PDU54-1500 1500 200 22.50 pdu54-2000 2000 400 30.00 pdu54-2500 2500 400 37.50 pdu54-3000 3000 500 45.00 note: any dash number between 100 and 3000 not shown is also available.
pdu54 doc #98004 data delay devices, inc. 2 3/18/98 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com application notes address update the pdu54 is a memory device. as such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. the timing restrictions are shown in figure 1. after the last signal edge to be delayed has appeared on the out pin, a minimum time, t oax , is required before the address lines can change. this time is given by the following relation: t oax = max { (a i - a i-1 ) * t inc , 0 } where a i-1 and a i are the old and new address codes, respectively. violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the out pin. the possibility of spurious signals persists until the required t oax has elapsed. input restrictions there are three types of restrictions on input pulse width and period listed in the ac characteristics table. the recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. the suggested conditions are those for which signals will propagate through the unit without significant distortion. the absolute conditions are those for which the unit will produce some type of output for a given input. when operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. however, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. in other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. please consult the technical staff at data delay devices if your application has specific high-frequency requirements. please note that the increment tolerances listed represent a design goal. although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. monotonicity is, however, guaranteed over all addresses. package dimensions pdu54-xx (commercial dip) pdu54-xxm (military dip) 1.270 .010 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 .380 max. .015 typ. .070 max. .018 typ. 1.100 .010 11 equal spaces each .100 .010 non-accumulative .580 max. .600 .005 .010 .002 lead material: nickel-iron alloy 42 tin plate 20 19 18 17 24 23 22 21
pdu5 4 doc #98004 data delay devices, inc. 3 3/18/98 3 mt. prospect ave. clifton, nj 07013 package dimensions ( cont?d) pdu54-xxc4 (commercial smd) pdu54-xxmc4 (military smd) 1.280 .020 .882 .005 .020 typ. .040 typ. .100 .090 1.100 .280 max. .590 max. .010 .002 .050 .010 .710 .005 .007 .005 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 device specifications table 1: ac characteristics parameter symbol min typ units total programmable delay td t 7 t inc inherent delay td 0 3.3 ns address to input setup time t ais 2.9 ns output to address change t oax see text absolute per in 20 % of td t input period suggested per in 40 % of td t recommended per in 200 % of td t absolute pw in 10 % of td t input pulse width suggested pw in 20 % of td t recommended pw in 100 % of td t table 2: absolute maximum ratings parameter symbol min max units notes dc supply voltage v ee -7.0 0.3 v input pin voltage v in v ee - 0.3 0.3 v storage temperature t strg -65 150 c lead temperature t lead 300 c 10 sec table 3: dc electrical characteristics (0c to 85c) parameter symbol min max units notes high level output voltage v oh -1.025 -0.880 v v ih = max,50 w to -2v low level output voltage v ol -1.810 -1.620 v v il = min, 50 w to -2v high level input voltage v ih -1.165 -0.880 v low level input voltage v il -1.810 -1.475 v high level input current i ih 340 m a v ih = max low level input current i il 0.5 m a v il = min
pdu54 doc #98004 data delay devices, inc. 4 3/18/98 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c load: 50 w to -2v supply voltage ( vcc): -4.5v 0.1v c load : 5pf 10% input pulse: standard 100k ecl threshold: (v oh + v ol ) / 2 levels (rising & falling) source impedance: 50 w max. rise/fall time: 1.0 ns max. (measured between 20% and 80%) pulse width: pw in = 10ns period: per in = 100ns note: the above conditions are for test only and do not in any way restrict the operation of the device. out out trig in ref trig test setup device under test (dut) oscilloscope pulse generator in address select timing diagram for testing t rise t fall per in pw in t rise t fall 20% 20% 50% 50% 80% 80% 50% 50% v ih v il v oh v ol input signal output signal
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